(1) Field of the Invention
The present invention relates to the manufacture of integrated circuit (IC) chips, and in particular to the forming of aluminum bumps in the packaging of IC chips.
(2) Description of the Related Art
Integrated circuits are formed on a silicon wafer which is then diced or cut to form individual die, also called chips, as is well known in the art. The circuits which are interconnected in each chip terminate at terminals on the chip. The appropriate chips are then interconnected with each other by bonding those terminals onto a card having its own interconnections. Depending upon the complexity and function of the final machine that is to be built, this first level package may in turn be interconnected with other first level cards by connecting the cards onto a second level package, usually called a board.
The chip level interconnection forming the first level package is usually performed using wirebonding (WB), tape automated bonding (TAB), or flip-chip solder connection, sometimes referred to as controlled collapse chip connection (C4). A detailed description of each of these interconnection schemes will not be given here so as to not obscure the key aspects of the present invention, and also, as they are not necessary to the understanding of the teachings of the present invention. Suffice it to say, however, that in each one of these schemes, a terminal, in the form of a cubical bump--as it will be described more fully later--is required to form the chip to chip interconnection at the first level of packaging.
A conventional bump structure of a semiconductor device and a method forming of the same is shown in FIGS. 1a-1d following Endo, et al., in U.S. Pat. No. 5,057,453. In prior art FIG. 1a, semiconductor substrate (10) is shown having an aluminum electrode pad (20). An insulating passivation film, layer (30) in the same FIG. 1a, is formed over the substrate and a partial opening is next formed in the insulation layer over the Al pad. A metal film, as barrier metal layer (40), is then deposited over passivation layer (30), including over pad (20) by using any number of conventional methods such as vapor deposition or sputtering.
Next, a photopolymerized high polymer dry film (50) is pressure-laminated on metal film (40). The dry film is patterned to form an opening with a size corresponding to a desired bump side length, at the position only above electrode pad (20). Then, using the patterned dry film as a plating mask, and metal film (40) as one of the electrodes, gold, Au, is selectively electroplated only within the opening of the dry film (50).
Next, the dry film is removed, and a cubical Au deposit (60) is obtained on metal film (40) above electrode pad (20), as shown in FIG. 1c. Subsequently, using the gold metal as a mask, metal film (40) is etched as shown in FIG. 1d. Thus, a semiconductor device with a gold bump (60) of a conventional structure is formed on metal film (40) above A1 electrode pad (20).
It will be noted in FIG. 1d, however, that when etching of metal film (40) is performed, there is usually an incursion of the etchants under gold bump (60) such that cavity (70), or an undercut, is formed. This can be detrimental in many ways. First, peel strength of the bump is degraded as the cross-sectional area of the interfacial area between the bump and the metal film is decreased. Secondly, cavity (70) can harbor contaminants which corrode the aluminum electrode. Endo discloses a method of forming a skirt extending outward from the bottom of the cubical bump to prevent the formation of cavity (70).
Gilton in U.S. Pat. No. 5,445,994 proposes a different method for forming custom planar metal bonding pad connectors. The method includes the steps of depositing a passivation layer on the bonding pads; forming a patterning layer by depositing a dielectric materials on the passivation layer; etching through the patterning layer and passivation layer to the bond pads using a first etch mask; etching a connector pattern in the patterning layer using a second etch mask; depositing a metal layer over the patterning layer; and then planarizing the metal layer to an endpoint of the pattering layer to form planar metal connectors.
Farnwoth, et al., provide a method for packaging semiconductor dice. In U.S. Pat. No. 5,593,927, the inventors use an additional protective layer and conductive traces on the die where the protective layer is formed with a tapered peripheral edge to facilitate insertion of die into a die holder.
It is disclosed later in the embodiments of the present invention a different method of forming bonding pads in the form of aluminum bumps which is especially suited for tape-automated-bonding of integrated circuit, IC chips in advanced packaging technology.